|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
this is information on a product in full production. june 2013 docid023353 rev 6 1/132 stm32f302xb stm32f302xc stm32f303xb stm32f303xc arm cortex-m4 32b mcu+fpu, up to 256kb flash+48kb sram 4 adcs, 2 dac ch., 7 comp, 4 pga, timers, 2.0-3.6 v operation datasheet - production data features ? core: arm ? cortex?-m4 32-bit cpu with fpu (72 mhz max), single-cycle multiplication and hw division, 90 dmips(from ccm) /1.25 dmips/mhz (dhrystone 2.1), dsp instruction and mpu (memory protection unit) ? operating conditions: ?v dd , v dda voltage range: 2.0 v to 3.6 v ? memories ? 128 to 256 kbytes of flash memory ? up to 40 kbytes of sram, with hw parity check implemented on the first 16 kbytes. ? routine booster: 8 kbytes of sram on instruction and data bus, with hw parity check (ccm) ? crc calculation unit ? reset and supply management ? power-on/power down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop and standby ?v bat supply for rtc and backup registers ? clock management ?4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x 16 pll option ? intern al 40 khz oscillator ? up to 87 fast i/os ? all mappable on external interrupt vectors ? several 5 v-tolerant ? 12-channel dma controller ? up to four adc 0.20 s (up to 39 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 v conversion range, separate analog supply from 2 to 3.6 v ? up to two 12-bit dac channels with analog supply from 2.4 to 3.6 v ? seven fast rail-to-rail analog comparators with analog supply from 2 to 3.6 v ? up to four operational amplifiers that can be used in pga mode, all terminal accessible with analog supply from 2.4 to 3.6 v ? up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensor s ? up to 13 timers ? one 32-bit timer and two 16-bit timers with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? up to two 16-bit 6-channel advanced-control timers, with up to 6 pwm channels, deadtime generation and emergency stop ? one 16-bit timer with 2 ic/ocs, 1 ocn/pwm, deadtime generation and emergency stop ? two 16-bit timers with ic/oc/ocn/pwm, deadtime generation and emergency stop ? two watchdog timers (independent, window) ? systick timer: 24-bit downcounter ? up to two 16-bit basic timers to drive the dac ? calendar rtc with alarm, periodic wakeup from stop/standby ? communication interfaces ? can interface (2.0b active) ?two i 2 c fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, wakeup from stop ? up to five usart/uarts (iso 7816 interface, lin, irda, modem control) ? up to three spis, two with multiplexed half/full duplex i2s interface, 4 to 16 programmable bit frame ? usb 2.0 full speed interface ? infrared transmitte r ? serial wire debug, cortex-m4 with fpu etm, jtag ? 96-bit unique id table 1. device summary reference part number stm32f302xx stm32f302cb, stm32f302cc, stm32f302rb, stm32f302rc, stm32f302vb, stm32f302vc stm32f303xx stm32f303cb, stm32f303cc, stm32f303rb, stm32f303rc, stm32f303vb, stm32f303vc lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp48 (7 7 mm) www.st.com
contents stm32f302xx/stm32f303xx 2/132 docid023353 rev 6 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 arm ? cortex?-m4 core with fpu with embedded flash and sram . . . 13 3.2 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 19 3.12 fast analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12.4 opamp reference voltage (vopamp) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15 fast comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16.1 advanced timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.2 general-purpose timers (tim2, tim3, tim4, tim15, tim16, tim17) . . 23 3.16.3 basic timers (tim6, tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 docid023353 rev 6 3/132 stm32f302xx/stm32f303xx contents 4 3.16.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 24 3.18 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.19 universal synchronous/asynchronous re ceiver transmitter (usart) . . . 27 3.20 universal asynchronous receiver transmitter (uart) . . . . . . . . . . . . . . . 27 3.21 serial peripheral interface (spi)/inter-integrated sound interfaces (i2s) . 27 3.22 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.23 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.24 infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.25 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.26 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.26.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.26.2 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 60 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 60 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 contents stm32f302xx/stm32f303xx 4/132 docid023353 rev 6 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.16 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.18 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.19 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.20 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.21 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 126 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 docid023353 rev 6 5/132 stm32f302xx/stm32f303xx list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f302xx/stm32f303xx family device featur es and peripheral counts. . . . . . . . . . . 10 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. stm32f302xx/stm32f303xx i 2 c implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6. usart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. stm32f302xx/stm32f303xx spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. capacitive sensing gpios available on st m32f302xx/stm32f303xx devices . . . . . . . . 30 table 9. no. of capacitive sensing channels available on stm32f302xx/stm32f303xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. stm32f302xx/stm32f303xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. alternate functions for port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 13. alternate functions for port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 14. alternate functions for port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. alternate functions for port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 16. alternate functions for port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 17. alternate functions for port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 18. stm32f302xx/stm32f303xx memory ma p and peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 19. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 20. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 21. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 22. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 23. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 24. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 25. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 26. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 table 27. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 28. typical and maximum current consumption from v dd supply at v dd = 3.6v . . . . . . . . . . . 63 table 29. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 64 table 30. typical and maximum v dd consumption in stop and standby modes. . . . . . . . . . . . . . . . 65 table 31. typical and maximum v dda consumption in stop and standby modes. . . . . . . . . . . . . . . 65 table 32. typical and maximum current consumption from v bat supply. . . . . . . . . . . . . . . . . . . . . . 66 table 33. typical current consumption in run mode, code with data processing running from flash 67 table 34. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 68 table 35. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 36. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 37. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 38. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 39. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 40. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 41. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 42. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 43. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 44. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 45. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 46. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 list of tables stm32f302xx/stm32f303xx 6/132 docid023353 rev 6 table 47. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 48. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 49. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 50. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 51. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 52. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 53. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 54. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 55. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 56. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 57. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 58. wwdg min-max timeout value @72 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 59. i2c timings specification (see i2c specification, rev.03, june 2007) . . . . . . . . . . . . . . . . . 95 table 60. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 61. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 62. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 63. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 64. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 65. usb: full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 table 66. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 67. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 68. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 table 69. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 70. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 71. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 72. operational amplifier characteristic s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 73. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 74. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 75. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 76. lqpf100 ? 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 119 table 77. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 121 table 78. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 123 table 79. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 80. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 81. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 docid023353 rev 6 7/132 stm32f302xx/stm32f303xx list of figures 7 list of figures figure 1. stm32f302xb/stm32f302xc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. stm32f303xb/stm32f303xc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5. stm32f302xx/stm32f303xx lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 6. stm32f302xx/stm32f303xx lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7. stm32f302xx/stm32f303xx lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 8. stm32f302xx/stm32f303xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 11. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 12. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 13. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) . . . . . . . . . . . 66 figure 14. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 15. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 16. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 17. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 18. hsi oscillator accuracy characte rization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 19. tc and tta i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 20. tc and tta i/o input characteri stics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 21. five volt tolerant (ft and ftf) i/o input char acteristics - cmos port. . . . . . . . . . . . . . . . . 89 figure 22. five volt tolerant (ft and ftf) i/o input charac teristics - ttl port . . . . . . . . . . . . . . . . . . . 89 figure 23. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 24. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 25. i 2 c bus ac waveforms and measurement ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 26. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 27. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 28. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 29. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 30. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 31. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 32. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 33. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 34. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 35. opamp voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 36. lqfp100 ? 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 119 figure 37. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 38. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 121 figure 39. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 40. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 123 figure 41. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 introduction stm32f302xx/stm32f303xx 8/132 docid023353 rev 6 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32f302xx/stm32f303xx microcontrollers. this stm32f302xx/stm32f303xx datasheet should be read in conjunction with the stm32f302xx/stm32f303xx reference manual. the reference manual is available from the stmicroelectronics website www.st.com. for information on the cortex?-m4 core with fpu please refer to: ? cortex?-m4 with fpu technical reference manual , available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp ?topic=/com.arm.doc.subset.cortexm.m4/ index.html ? stm32f3xxx and stm32f4xxx cortex-m4 programming manual (pm0214) available from the www.st.com website at the following address: http://www.st.com/internet /com/technical_ resources/ technical_literature/progr amming_manual/dm00046982.pdf docid023353 rev 6 9/132 stm32f302xx/stm32f303xx description 53 2 description the stm32f302xx/stm32f303xx family is based on the high-performance arm ? cortex?-m4 32-bit risc core with fpu oper ating at a frequency of up to 72 mhz, and embedding a floating point unit (fpu), a memory protection unit (mpu) and an embedded trace macrocell (etm). the fam ily incorporates high-speed embedded memories (up to 256 kbytes of flash memory, up to 48 kbytes of sram) and an extensive range of enhanced i/os and peripheral s connected to two apb buses. the devices offer up to four fast 12-bit adcs (5 msps), up to seven comparators, up to four operational amplifiers, up to two dac channels, a low-power rtc, up to five general- purpose 16-bit timers, one general-purpose 32-bi t timer, and two timers dedicated to motor control. they also feature standard and advanced communication interfaces: up to two i 2 cs, up to three spis (two spis are wit h multiplexed full- duplex i2ss on stm32f303xb/stm32f303xc devices), three us arts, up to two uarts, can and usb. to achieve audio class accuracy, the i2s peri pherals can be clocked via an external pll. the stm32f302xx/stm32f303xx family operates in the -40 to +85 c and -40 to +105 c temperature ranges from a 2.0 to 3.6 v powe r supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f302xx/stm32f303xx family offers devices in three packages ranging from 48 pins to 100 pins. the set of included peripherals changes with the device chosen. description stm32f302xx/stm32f303xx 10/132 docid023353 rev 6 table 2. stm32f302xx/stm32f303xx family device features and peripheral counts peripheral stm32f 302cx stm32f 302rx stm32f 302vx stm32f 303cx stm32f 303rx stm32f 303vx flash (kbytes) 128 256 128 256 128 256 128 256 128 256 128 256 sram (kbytes) on data bus 24 32 24 32 24 32 32 40 32 40 32 40 ccm (core coupled memory) ram (kbytes) n/a 8 timers advanced control 1 (16-bit) 2 (16-bit) general purpose 5 (16-bit) 1 (32-bit) basic 1 (16-bit) 2 (16-bit) comm. interfaces spi(i2s) (1) 33(2) i 2 c2 usart 3 uart 0 2 0 2 can 1 usb 1 gpios normal i/os (tc, tta) 20 27 45 20 27 45 5 volts tolerant i/os (ft, ftf) 17 25 42 17 25 42 dma channels 12 capacitive sensing channels 17 18 24 17 18 24 12-bit adcs 2 4 12-bit dac channels 1 2 analog comparator 4 7 operational amplifiers 2 4 cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: - 40 to 85 c / - 40 to 105 c junction temperature: - 40 to 125 c packages lqfp48 lqfp64 lqfp100 lqfp48 lqfp64 lqfp100 1. in stm32f303xb/stm32f303xc devices the spi interfaces can work in an exclusive way in either the spi mode or the i 2 s audio mode. docid023353 rev 6 11/132 stm32f302xx/stm32f303xx description 53 figure 1. stm32f302xb/s tm32f302xc block diagram 1. af: alternate function on i/o pins. msv18959v6 touch sensing controller ahb decoder timer 16 2 channels,1 comp channel, brk as af timer 17 timer 1 / pwm spi1 mosi, miso, sck,nss as af usart1 rx, tx, cts, rts, smartcard as af winwatchdog busmatrix mpu/fpu cortex m4 cpu f max : 72 mhz nvic gp dma1 7 channels flash interface obl flash 256 kb 64 bits jtrst jtdi jtck/swclk jtms/swdio jtdo as af power voltage reg. 3.3 v to 1.8v v dd18 supply supervision por /pdr pvd por reset int. v ddio = 2 to 3.6 v v ss nreset v dda v ssa ind. wdg32k standby interface pll @v ddio @v dda xtal osc 4 -32 mhz reset & clock control ahbpclk apbp1clk apbp2clk ahb2 apb2 ahb2 apb1 crc apb1 f max = 36 mhz apb2 f max = 72 mhz gpio port a gpio port b gpio port c gpio port d gpio port e osc_in osc_out spi3 scl, sda, smba as af usart2 scl, sda, smba as af usart3 rc ls timer6 timer 4 spi2 12bit dac1 if @v dda timer2 (32-bit/pwm) pa[15:0] pb[15:0] pc[15:0] mosi, miso, sck, nss as af 4 channels, etr as af usb_dp, usb_dm dac1_ch1 as af hclk fclk usartclk rc hs 8mhz sram 40 kb etm trace/trig swjtag tpiu ibus tradeclk traced[0-3] as af dbus system gp dma2 5 channels 12-bit adc1 12-bit adc2 temp. sensor v ref+ v ref- timer 15 ext.it wkup xx af 1 channel, 1 comp channel, brk as af 1 channel, 1 comp channel, brk as af 4 channels, 4 comp channels, etr, brk as af gpio port f pd[15:0] pe[15:0] usb sram 512b pf[7:0] if i2cclk adc sar 1/2/3/4 clk @v ddio @v dda @vsw xtal 32khz osc32_in osc32_out v bat = 1.65v to 3.6v rtc awu backup reg (64byte) backup interface anti-tamp timer 3 uart4 uart5 i2c1 i2c2 bx can & 512b sram usb 2.0 fs opamp1 opamp2 @v dda inxx / outxx inxx / outxx interface syscfg ctl gp comparator 6 gp comparator 4 gp comparator 2 can tx, can rx 4 channels, etr as af 4 channels, etr as af rx, tx, cts, rts, as af rx, tx, cts, rts, as af rx, tx as af rx, tx as af @v dda xx ins, 4 outs as af xx groups of 4 channels as af mosi, miso, sck, nss as af gp comparator 1 description stm32f302xx/stm32f303xx 12/132 docid023353 rev 6 figure 2. stm32f303xb/s tm32f303xc block diagram 1. af: alternate function on i/o pins. ms18960v4 touch sensing controller timer 16 2 channels,1 comp channel, brk as af timer 17 timer 1 / pwm timer 8 / pwm 4 channels, 4 comp channels, etr, brk as af spi1 mosi, miso, sck,nss as af usart1 rx, tx, cts, rts, smartcard as af winwatchdog busmatrix mpu/fpu cortex m4 cpu f max : 72 mhz nvic gp dma1 7 channels ccm ram 8kb flash interface obl flash 256 kb 64 bits jtrst jtdi jtck/swclk jtms/swdio jtdo as af power voltage reg. 3.3 v to 1.8v v dd18 supply supervision por /pdr pvd por reset int. v ddio = 2 to 3.6 v v ss nreset v dda v ssa ind. wdg32k standby interface pll @v ddio @v dda xtal osc 4 -32 mhz reset & clock control ahbpclk apbp1clk apbp2clk ahb2 apb2 ahb2 apb1 crc apb1 f max = 36 mhz apb2 f max = 72 mhz gpio port a gpio port b gpio port c gpio port d gpio port e osc_in osc_out spi3/i2s scl, sda, smba as af usart2 scl, sda, smba as af usart3 rc ls timer6 timer 4 spi2/i2s 12bit dac1 if @v dda timer2 (32-bit/pwm) pa[15:0] pb[15:0] pc[15:0] mosi/sd, miso/ext_sd, sck/ck, nss/ws, mclk as af 4 channels, etr as af usb_dp, usb_dm dac1_ch1 as af hclk fclk usartclk rc hs 8mhz sram 40 kb etm trace/trig swjtag tpiu ibus tradeclk traced[0-3] as af dbus system gp dma2 5 channels 12-bit adc1 12-bit adc2 if temp. sensor v ref+ v ref- timer 15 ext.it wkup xx af 1 channel, 1 comp channel, brk as af 1 channel, 1 comp channel, brk as af 4 channels, 4 comp channels, etr, brk as af gpio port f pd[15:0] pe[15:0] timer7 usb sram 512b pf[7:0] 12-bit adc3 if 12-bit adc4 i2cclk adc sar 1/2/3/4 clk @v ddio @v dda @vsw xtal 32khz osc32_in osc32_out v bat = 1.65v to 3.6v rtc awu backup reg (64byte) backup interface anti-tamp timer 3 uart4 uart5 i2c1 i2c2 bx can & 512b sram usb 2.0 fs dac1_ch2 as af opamp1 opamp2 opamp3 opamp4 @v dda inxx / outxx inxx / outxx inxx / outxx inxx / outxx interface syscfg ctl gp comparator 7 p gp comparator... gp comparator 1 can tx, can rx 4 channels, etr as af 4 channels, etr as af mosi/sd, miso/ext_sd, sck/ck, nss/ws, mclk as af rx, tx, cts, rts, as af rx, tx, cts, rts, as af rx, tx as af rx, tx as af @v dda xx ins, 7 outs as af xx groups of 4 channels as af ahb2 ahb3 docid023353 rev 6 13/132 stm32f302xx/stm32f303xx functional overview 53 3 functional overview 3.1 arm ? cortex?-m4 core with fpu with embedded flash and sram the arm cortex-m4 processor with fpu is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm cortex-m4 32-bit risc processor with fpu features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the stm32f302xx/ stm32f303xx family is compatible with all arm tools and software. figure 1 and figure 2 show the general block diagrams of the stm32f302xx/stm32f303xx family devices. 3.2 memory protection unit (mpu) the memory protection unit (mpu) is used to se parate the processing of tasks from the data protection. the mpu can manage up to 8 protection areas that can all be further divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the memory protection unit is especially help ful for applications w here some critical or certified code has to be protected against th e misbehavior of other tasks. it is usually managed by an rtos (real-time operating system). if a program accesses a memory location that is prohibited by the mpu, the rt os can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 3.3 embedded flash memory all stm32f302xx/stm32f303xx devices feat ure up to 256 kbytes of embedded flash memory available for storing programs and data. the flash memory access time is adjusted to the cpu clock frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). functional overview stm32f302xx/stm32f303xx 14/132 docid023353 rev 6 3.4 embedded sram stm32f302xx/stm32f303xx devices feature up to 48 kbytes of embedded sram with hardware parity check. the memory can be acce ssed in read/write at cpu clock speed with 0 wait states, allowing the cpu to achieve 90 dhrystone mips at 72 mhz (when running code from the ccm (core coupled memory) ram). ? 8 kbytes of ccm ram on stm32f303xx devices mapped on both instruction and data bus, used to execute critical routines or to access data (parity check on all of ccm ram). ? 40 kbytes of sram mapped on the data bus (p arity check on first 16 kbytes of sram). 3.5 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart2 (pd5 /pd6) or usb (pa11/pa12) through dfu (device firmware upgrade). 3.6 cyclic redund ancy check (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compar ed with a reference signature generated at linktime and stored at a given memory location. docid023353 rev 6 15/132 stm32f302xx/stm32f303xx functional overview 53 3.7 power management 3.7.1 power supply schemes ? v ss , v dd = 2.0 to 3.6 v : external power supply for i/os and the internal regulator. it is provided externally through v dd pins. ? v ssa , v dda = 2.0 to 3.6 v: external analog power supply for adc, dacs, comparators operational amplifiers, reset blocks, rcs an d pll (minimum voltage to be applied to v dda is 2.4 v when the dacs and operational amplifiers are used). the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.7.2 power supply supervisor the device has an integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the app lication design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.7.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr), and power-down. ? the mr mode is used in the nominal regulation mode (run) ? the lpr mode is used in stop mode. ? the power-down mode is used in standby mo de: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the voltage regulator is always enabled after reset. it is disabled in standby mode. functional overview stm32f302xx/stm32f303xx 16/132 docid023353 rev 6 3.7.4 low-power modes the stm32f302xx/stm32f303xx supports three low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the usb wakeup on stm32f303xb/stm32f303xc devices, the rt c alarm, compx, i2cx or u(s)artx. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin or an rtc alarm occurs. note: the rtc, the iwdg and the corresponding clock sources are not stopped by entering stop or standby mode. docid023353 rev 6 17/132 stm32f302xx/stm32f303xx functional overview 53 3.8 clocks and startup system clock selection is perf ormed on startup, however the in ternal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domain s. the maximum fr equency of the ah b and the high speed apb domains is 72 mhz, while the maximum allowed fr equency of t he low speed apb domain is 36 mhz. functional overview stm32f302xx/stm32f303xx 18/132 docid023353 rev 6 figure 3. clock tree /32 4-32 mhz hse osc osc_in osc_out osc32_in osc32_out 8 mhz hsi rc iwdgclk to iwdg pll x2,x3,.. x16 pllmul mco main clock output ahb /2 pllclk hsi hse apb1 prescaler /1,2,4,8,16 hclk pllclk to ahb bus, core, memory and dma lse lsi hsi hsi hse to rtc pllsrc sw mco /8 sysclk rtcclk rtcsel[1:0] sysclk to tim 2,3,4,6,7 if (apb1 prescaler =1) x1 else x2 flitfclk to flash programming interface lsi to i2cx (x = 1,2) to u(s)artx (x = 2..5) lse hsi sysclk /2 pclk1 sysclk hsi pclk1 ms19989v4 to i2sx (x = 2,3) usbclk to usb interface to cortex system timer fhclk cortex free running clock to apb1 peripherals ahb prescaler /1,2,..512 css /2,/3,... /16 lse osc 32.768khz lsi rc 40khz usb prescaler /1,1.5 apb2 prescaler /1,2,4,8,16 to tim 15,16,17 if (apb2 prescaler =1) x1 else x2 to usart1 lse hsi sysclk pclk2 pclk2 to apb2 peripherals tim1/8 adc prescaler /1,2,4 to adcxy (xy = 12, 34) adc prescaler /1,2,4,6,8,10,12,16, 32,64,128,256 i2ssrc sysclk ext. clock i2s_ckin x2 docid023353 rev 6 19/132 stm32f302xx/stm32f303xx functional overview 53 3.9 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable except for analog inputs. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allows i/o toggling up to 36 mhz. 3.10 direct memory access (dma) the flexible general-purpose dma is able to manage memory-to-memory, peripheral-to- memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrup ts when the controller reaches the end of the buffer. each of the 12 dma channels is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose timers, dac and adc. 3.11 interrupts and events 3.11.1 nested vectored in terrupt controller (nvic) the stm32f302xx/stm32f303xx devices embed a nested vectored interrupt controller (nvic) able to handle up to 66 maskable interrupt channels and 16 priority levels. the nvic benefits are the following: ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. functional overview stm32f302xx/stm32f303xx 20/132 docid023353 rev 6 3.12 fast analog-to-digital converter (adc) up to four fast analog-to-dig ital converters 5 msps, with se lectable resolution between 12 and 6 bit, are embedded in the stm32f302xx/stm32f303xx family devices. the adcs have up to 39 external channels. some of the external channels are shared between adc1&2 and between adc3&4, performing conver sions in single-shot or scan modes. in scan mode, automatic conversion is performe d on a selected group of analog inputs. the adcs have also internal channels: temp erature sensor connected to adc1 channel 16, v bat/2 connected to adc1 channel 17, voltage reference v refint connected to the 4 adcs channel 18, vopamp1 connected to adc1 channel 15, vopamp2 connected to adc2 channel 17, vopamp3 connected to adc3 channel 17, vopamp4 connected to adc4 channel 17. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold ? single-shunt phase current reading techniques. the adc can be served by the dma controller. an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers and the advanced-control timers (tim1 on all devices and tim8 on stm32f30 3xb/stm32f303xc devices) can be internally connected to the adc start trigger and injection trigger, respectively, to allow the application to synchronize a/d conversion and timers. 3.12.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.12.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally connected to th e adc_in18 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the syste m memory area. it is accessible in read-only mode. docid023353 rev 6 21/132 stm32f302xx/stm32f303xx functional overview 53 3.12.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc_in17. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. 3.12.4 opamp reference voltage (vopamp) every opamp reference voltage can be measured using a corresponding adc internal channel: vopamp1 connected to adc1 ch annel 15, vopamp2 connected to adc2 channel 17, vopamp3 connected to adc3 channel 17, vopamp4 connected to adc4 channel 17. 3.13 digital-to-analog converter (dac) up to two 12-bit buffered dac channels can be used to convert digital signals into analog voltage signal outputs. the chosen design st ructure is composed of integrated resistor strings and an amplifier in inverting configuration. this digital interface supp orts the following features: ? up to two dac output channels on stm32f303xb/stm32f303xc devices ? 8-bit or 10-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability on stm32f303xb/stm32f303xc devices ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions on stm32f303xb/stm32f303xc devices ? dma capability (for each channel on stm32f303xb/stm 32f303xc devices) ? external triggers for conversion ? input voltage reference vref+ 3.14 operational amplifier (opamp) the stm32f302xx/stm32f303xx embeds up to four operational amplifiers with external or internal follower rout ing and pga capability (or even amp lifier and filter capability with external components). when an operational amplifier is selected, an external adc channel is used to enable output measurement. the operational amplifier features: ? 8.2 mhz bandwidth ? 0.5 ma output capability ? rail-to-rail input/output ? in pga mode, the gain can be programmed to be 2, 4, 8 or 16. functional overview stm32f302xx/stm32f303xx 22/132 docid023353 rev 6 3.15 fast comparators (comp) the stm32f302xx/stm32f303xx devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or exte rnal), hysteresis and speed (low speed for low power) and with selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output pin ? internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to table 26: embedded internal reference voltage on page 62 for the value and precision of the internal reference voltage. all comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator 3.16 timers and watchdogs the stm32f302xx/stm32f303xx includes up to two advanced control timers, up to 6 general-purpose timers, two basic timers, two watchdog timers and a systick timer. the table below compares the features of the ad vanced control, general purpose and basic timers. table 3. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced tim1, tim8 (on stm32f303xb /stm32f303x c devices only) 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general- purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim15 16-bit up any integer between 1 and 65536 yes 2 1 general- purpose tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, tim7 (on stm32f303xb /stm32f303x c devices only) 16-bit up any integer between 1 and 65536 yes 0 no docid023353 rev 6 23/132 stm32f302xx/stm32f303xx functional overview 53 3.16.1 advanced time rs (tim1, tim8) the advanced-control timers (tim1 on all devices and tim8 on stm32f303xb/stm32f303xc devices) can each be seen as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead-times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or cent er-aligned modes) with full modulation capability (0- 100%) ? one-pulse mode output in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose tim timers (described in section 3.16.2 using the same architecture, so t he advanced-control timers can work together with the tim timers via the timer link feature for synchronization or event chaining. 3.16.2 general-purpose timers (tim2, tim3, tim4, tim15, tim16, tim17) there are up to six synchronizable general-purpose timers embedded in the stm32f302xx/stm32f303xx (see table 3 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. ? tim2, 3, and tim4 these are full-featured general-purpose timers: ? tim2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler ? tim3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers. these timers all feature 4 independent chan nels for input capture/output compare, pwm or one-pulse mode output. they can work together, or with the other general- purpose timers via the timer link featur e for synchronization or event chaining. the counters can be frozen in debug mode. all have independent dma request generat ion and support quadrature encoders. ? tim15, 16 and 17 these three timers general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. functional overview stm32f302xx/stm32f303xx 24/132 docid023353 rev 6 3.16.3 basic timers (tim6, tim7) these timers are mainly used for dac trigge r generation. they can also be used as a generic 16-bit time base. 3.16.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standb y modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.16.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.16.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source 3.17 real-time clock (rtc ) and backup registers the rtc and the 16 backup registers are supplied through a switch that takes power from either the v dd supply when present or the v bat pin. the backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when v dd power is not present. they are not reset by a system or power rese t, or when the device wakes up from standby mode. docid023353 rev 6 25/132 stm32f302xx/stm32f303xx functional overview 53 the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? automatic correction for 28, 29 (leap year), 30 and 31 days of the month. ? two programmable alarms with wake up fr om stop and standb y mode capability. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy. ? three anti-tamper detection pins with programmable filter. the mcu can be woken up from stopand standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? 17-bit auto-reload counter for periodic interrupt with wakeup from stop/standby capability. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32. functional overview stm32f302xx/stm32f303xx 26/132 docid023353 rev 6 3.18 inter-integrated circuit interface (i 2 c) up to two i 2 c bus interfaces can operate in multim aster and slave modes. they can support standard (up to 100 khz), fast (up to 400 khz) and fast mode + (up to 1 mhz) modes. both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, they provide hard ware support for sm bus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) gener ation/verification, timeouts verifications and alert protocol management. they also have a clock domain independent from the cpu clock, allowing the i2cx (x=1,2) to wake up the mcu from stop mode on address match. the i2c interfaces can be served by the dma controller. refer to table 5 for the features available in i2c1 and i2c2. table 4. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. table 5. stm32f302xx/stm32f303xx i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 7-bit addressing mode x x 10-bit addressing mode x x standard mode (up to 100 kbit/s) x x fast mode (up to 400 kbit/s) x x fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x x independent clock x x smbus x x wakeup from stop x x docid023353 rev 6 27/132 stm32f302xx/stm32f303xx functional overview 53 3.19 universal synchronous/asynch ronous receiver transmitter (usart) the stm32f302xx/stm32f303xx devices have three embedded universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3). the usart interfaces are able to communicate at speeds of up to 9 mbits/s. they provide hardware management of the ct s and rts signals, they support irda sir endec, the multiprocessor communication mode, the single-wire half-duplex communication mode and have li n master/slave capability. the usart interfaces can be served by the dma controller. 3.20 universal asynchronous receiver transmitter (uart) the stm32f302xx/stm32f303xx devices have 2 embedded universal asynchronous receiver transmitters (uart4, and uart5) . the uart interfaces support irda sir endec, multiprocessor comm unication mode and single-wire half-duplex communication mode. the uart4 interface can be served by the dma controller. refer to table 6 for the features available in all u(s)arts interfaces. 3.21 serial peripheral interface (spi)/inter-integrated sound interfaces (i2s) up to three spis are able to communicate up to 18 mbits/s in slave and master modes in full-duplex and half-duplex communication mo des. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. table 6. usart features usart modes/features (1) usart1 usart2 usart3 uart4 uart5 hardware flow control for modem x x x continuous communication using dma x x x x multiprocessor communication x x x x x synchronous mode x x x smartcard mode x x x single-wire half-duplex communication x x x x x irda sir endec block x x x x x lin mode xxxxx dual clock domain and wakeup from stop mode x x x x x receiver timeout interrupt xxxxx modbus communication x x x x x auto baud rate detection x x x driver enable x x x 1. x = supported. functional overview stm32f302xx/stm32f303xx 28/132 docid023353 rev 6 two standard i2s interfaces (multiplexed with spi2 and spi3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. they can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by 8-bit programmable linear prescaler. when operating in master mode it can output a clo ck for an external audio component at 256 times the sampling frequency. refer to table 7 for the features available in spi1, spi2 and spi3. 3.22 controller area network (can) the can is compliant with specif ications 2.0a and b (active) wit h a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 3.23 universal serial bus (usb) the stm32f302xx/stm32f303xx devices embed an usb device peripheral compatible with the usb full-speed 12 mbs. the usb interface implements a full-speed (12 mbit/s) function interface. it has software-configurable endpoint setting and suspend/resume support. the dedicated 48 mhz clock is gener ated from the internal main pll (the clock source must use a hse crystal oscillator) . the usb has a dedicated 512-bytes sram memory for data transmission and reception. table 7. stm32f302xx/stm32f303xx spi/i2s implementation spi features (1) 1. x = supported. spi1 spi2 spi3 hardware crc calculation x x x rx/tx fifo x x x nss pulse mode x x x i2s mode x x ti mode xxx docid023353 rev 6 29/132 stm32f302xx/stm32f303xx functional overview 53 3.24 infrared transmitter the stm32f302xx/stm32f303xx devices provide an infrared transmitter solution. the solution is based on internal connections between tim16 and ti m17 as shown in the figure below. tim17 is used to provide the carrier frequenc y and tim16 provides the main signal to be sent. the infrared output signal is available on pb9 or pa13. to generate the infrared remote control sign als, tim16 channel 1 and tim17 channel 1 must be properly configured to generate correct waveforms. all standard ir pulse modulation modes can be obtained by programming t he two timers output compare channels. figure 4. infrared transmitter 3.25 touch sensing controller (tsc) the stm32f302xx/stm32f303xx devices provide a simple solution for adding capacitive sensing functionality to any application. thes e devices offer up to 24 capacitive sensing channels distributed over 8 analog i/o groups. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). the capacitive variation introduced by the finger (or any conduct ive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor unt il the voltage across this capa citor has reached a specific threshold. to limit the cpu bandwidth usage th is acquisition is dire ctly managed by the hardware touch sensing controller and only r equires few external components to operate. the touch sensing controller is fully supported by the stmtouch touch sensing firmware library which is free to use and allows touch se nsing functionality to be implemented reliably in the end application. timer 16 (for envelop) timer 17 (for carrier) oc oc pb9/pa13 ms30365v1 functional overview stm32f302xx/stm32f303xx 30/132 docid023353 rev 6 table 8. capacitive sensing gpios available on stm32f302xx/stm32f303xx devices group capacitive sensing signal name pin name group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 5 tsc_g5_io1 pb3 tsc_g1_io2 pa1 tsc_g5_io2 pb4 tsc_g1_io3 pa2 tsc_g5_io3 pb6 tsc_g1_io4 pa3 tsc_g5_io4 pb7 2 tsc_g2_io1 pa4 6 tsc_g6_io1 pb11 tsc_g2_io2 pa5 tsc_g6_io2 pb12 tsc_g2_io3 pa6 tsc_g6_io3 pb13 tsc_g2_io4 pa7 tsc_g6_io4 pb14 3 tsc_g3_io1 pc5 7 tsc_g7_io1 pe2 tsc_g3_io2 pb0 tsc_g7_io2 pe3 tsc_g3_io3 pb1 tsc_g7_io3 pe4 tsc_g3_io4 pb2 tsc_g7_io4 pe5 4 tsc_g4_io1 pa9 8 tsc_g8_io1 pd12 tsc_g4_io2 pa10 tsc_g8_io2 pd13 tsc_g4_io3 pa13 tsc_g8_io3 pd14 tsc_g4_io4 pa14 tsc_g8_io4 pd15 table 9. no. of capacitive sensing channels available on stm32f302xx/stm32f303xx devices analog i/o group number of capacitive sensing channels stm32f30xvx stm32f30xrx stm32f30xcx g1 3 3 3 g2 3 3 3 g3 3 3 2 g4 3 3 3 g5 3 3 3 g6 3 3 3 g7 3 0 0 g8 3 0 0 number of capacitive sensing channels 24 18 17 docid023353 rev 6 31/132 stm32f302xx/stm32f303xx functional overview 53 3.26 development support 3.26.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared re spectively with swdio and swclk and a specific sequence on the tms pin is us ed to switch between jtag-dp and sw-dp. 3.26.2 embedded trace macrocell? the arm embedded trace ma crocell provides a greater visib ility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f302xx/stm32f303xx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using a high- speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools. pinouts and pin description stm32f302xx/stm32f303xx 32/132 docid023353 rev 6 4 pinouts and pin description figure 5. stm32f302xx/stm32f303xx lqfp48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 21 22 23 24 17 18 19 20 2 3 4 5 6 7 8 9 10 11 vbat pc14/osc32_in pc15/osc32_out nrst vssa/vref- vdda/vref+ pa0 pa1 pa2 vdd_1 vss_1 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 vdd_3 vss_3 pa13 pa12 pa11 pa10 pa 9 pa 8 pb15 pb14 pb13 pb12 pa 3 pa 4 pa 5 pa6 pa7 pb0 pb1 pb2 pb10 vss_2 pb11 vdd_2 pf0/osc_in pf1/osc_out pc13 12 1 . 4 7 , 1 & |